CMOS Realization of All-Positive Pinched Hysteresis Loops
| dc.contributor.author | Maundy, B. J. | |
| dc.contributor.author | Elwakil, A. S. | |
| dc.contributor.author | Psychalinos, C. | |
| dc.date.accessioned | 2018-09-27T11:16:29Z | |
| dc.date.available | 2018-09-27T11:16:29Z | |
| dc.date.issued | 2017-08-06 | |
| dc.date.updated | 2018-09-27T11:16:29Z | |
| dc.description.abstract | Two novel nonlinear circuits that exhibit an all-positive pinched hysteresis loop are proposed. These circuits employ two NMOS transistors, one of which operates in its triode region, in addition to two first-order filter sections. We show the equivalency to a charge-controlled resistance (memristance) in a decremental state via detailed analysis. Simulation and experimental results verify the proposed theory. | |
| dc.description.version | Peer Reviewed | |
| dc.identifier.citation | B. J. Maundy, A. S. Elwakil, and C. Psychalinos, “CMOS Realization of All-Positive Pinched Hysteresis Loops,” Complexity, vol. 2017, Article ID 7863095, 15 pages, 2017. doi:10.1155/2017/7863095 | |
| dc.identifier.doi | http://dx.doi.org/10.1155/2017/7863095 | |
| dc.identifier.doi | http://dx.doi.org/10.11575/PRISM/33018 | |
| dc.identifier.uri | http://hdl.handle.net/1880/108082 | |
| dc.language.rfc3066 | en | |
| dc.rights.holder | Copyright © 2017 B. J. Maundy et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. | |
| dc.title | CMOS Realization of All-Positive Pinched Hysteresis Loops | |
| dc.type | journal article |