CMOS Realization of All-Positive Pinched Hysteresis Loops

dc.contributor.authorMaundy, B. J.
dc.contributor.authorElwakil, A. S.
dc.contributor.authorPsychalinos, C.
dc.date.accessioned2018-09-27T11:16:29Z
dc.date.available2018-09-27T11:16:29Z
dc.date.issued2017-08-06
dc.date.updated2018-09-27T11:16:29Z
dc.description.abstractTwo novel nonlinear circuits that exhibit an all-positive pinched hysteresis loop are proposed. These circuits employ two NMOS transistors, one of which operates in its triode region, in addition to two first-order filter sections. We show the equivalency to a charge-controlled resistance (memristance) in a decremental state via detailed analysis. Simulation and experimental results verify the proposed theory.
dc.description.versionPeer Reviewed
dc.identifier.citationB. J. Maundy, A. S. Elwakil, and C. Psychalinos, “CMOS Realization of All-Positive Pinched Hysteresis Loops,” Complexity, vol. 2017, Article ID 7863095, 15 pages, 2017. doi:10.1155/2017/7863095
dc.identifier.doihttp://dx.doi.org/10.1155/2017/7863095
dc.identifier.doihttp://dx.doi.org/10.11575/PRISM/33018
dc.identifier.urihttp://hdl.handle.net/1880/108082
dc.language.rfc3066en
dc.rights.holderCopyright © 2017 B. J. Maundy et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
dc.titleCMOS Realization of All-Positive Pinched Hysteresis Loops
dc.typejournal article

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