Low power designs in cmos digital imaging systems

Abstract

First, a low power imager with dual analog power supply 1.8V and 1.1 V during integration and readout stages is proposed. The supply voltage for each 8x8 block depends on the estimated variance within the block. The imager is more efficient for predominant-background pictures. According to simulation, up to 37% of power consumption can be saved while PSNR loss is less than 1.5 dB. Then, a low power CMOS imaging system with "smart" image capture and adaptive complexity 2D-DCT calculation is proposed. The DCT calculation has adaptive complexity according to block types estimated during image capture. The image sensor with block type decision circuit is implemented in TSMC 0.18 ?m technology. The adaptive complexity 2DDCT calculation is implemented based on Cyclone EP1C20F400C8 device. Up to 46% of the power can be saved during compression for predominant-background images, while no extra image quality degradation occurs comparing with traditional compressions.